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ISL29012
Data Sheet December 10, 2008 FN6476.1
Light-to-Digital Output Sensor with High Sensitivity, Gain Selection, Interrupt Function and I2C BusTM
The ISL29012 is an integrated light sensor with I2C (SMBus Compatible) interface. It has an internal signed 15-bit integrating type ADC designed based on the charge-balancing A/D conversion technique. This ADC is capable of rejecting 50Hz and 60Hz flicker caused by artificial light sources. The lux range select feature allows the user to program the lux range for optimized counts/lux. In normal operation, power consumption is typically 250A. Furthermore, a power-down mode can be controlled by software via the I2C interface, reducing power consumption to less than 1A. The ISL29012 supports a hardware interrupt that remains asserted low until the host clears it through I2C interface. Designed to operate on supplies from 2.5V to 3.3V, the ISL29012 is specified for operation over the -40C to +85C ambient temperature range.
Features
* Range Select Via I2C - Range 1 = 0.5 lux to 2,000 lux - Range 2 = 0.5 lux to 8,000 lux - Range 3 = 0.5 lux to 32,000 lux - Range 4 = 0.5 lux to 128,000 lux * Human Eye Response (540nm Peak Sensitivity) * Temperature Compensated * Signed 15-bit Resolution * Adjustable Resolution: Up to 20 Counts per lux * User-programmable Upper and Lower Threshold Interrupt * Simple Output Code, Directly Proportional to lux * IR + UV Rejection * 50Hz/60Hz Rejection * 2.5V to 3.3V Supply * 6 Ld ODFN (2.1mmx2mm) * Pb-Free (RoHS compliant)
Ordering Information
PART NUMBER (Note) ISL29012IROZ-T7* ISL29012IROZ-EVALZ TEMP. RANGE (C) -40 to +85 PACKAGE (Pb-Free) 6 Ld ODFN PKG. DWG. # L6.2x2.1
* Operating Temperature Range: -40C to +85C * I2C and SMBus Compatible
Applications
* Display and Keypad Backlight Dimming - Mobile Devices: Smart phone, PDA, and GPS - Computing Devices: Notebook PC, UMPC Web Pod - Consumer Devices: LCD-TV, Digital Picture Frame and Digital Cameras * Industrial and Medical Light Sensing
Evaluation Board
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout Block Diagram
VDD 1 GAIN/RANGE INT TIME SHDN VDD 1 COMMAND REGISTER DATA REGISTER I2C 5 SCL 6 SDA GND 2 REXT 3
ISL29012 (6 LD ODFN) TOP VIEW
6 SDA 5 SCL 4 INT
LIGHT DATA PROCESS PHOTODIODE ARRAY IREF FOSC
INTEGRATING ADC
EXT TIMING INT 216 COUNTER
*EXPOSED PAD CAN BE CONNECTED TO GND OR ELECTRICALLY ISOLATED
INTERRUPT
4 INT
3 REXT
2 GND ISL29012
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. I2C Bus is a registered trademark owned by NXP Semiconductors Netherlands, B.V Copyright (c) Intersil Americas Inc. 2008. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL29012
Absolute Maximum Ratings (TA = +25C)
VDD Supply Voltage between VDD and GND . . . . . . . . . . . . . 3.6V I2C Bus (SCL, SDA) and INT Pin Voltage . . . . . . . . . . -0.2V to 5.5V I2C Bus (SCL, SDA) Pin Current . . . . . . . . . . . . . . . . . . . . . <10mA REXT Pin Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to VDD ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) 6 Lead ODFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +90C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-40C to +100C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER Ee-max VDD IDD IDD1 fOSC1 fOSC2 fI2C DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 VREF VTL VTH ISDA IINT NOTES:
VDD = 3V, TA = +25C, REXT = 100k, unless otherwise specified. Internal Timing Mode operation (See "Principles of Operation" on page 3). CONDITION @ Gain/Range = 4, and REXT = 25k 2.5 0.25 Software disabled Gain/Range = 1 or 2 Gain/Range = 3 or 4 308 616 0.1 342 684 1 to 400 E = 0 lux, Gain/Range = 1 0 32767 E = 300 lux, fluorescent light, Gain/Range = 1 (Note 2) E = 300 lux, fluorescent light, Gain/Range = 2 (Note 2) E = 300 lux, fluorescent light, Gain/Range = 3 (Note 2) E = 300 lux, fluorescent light, Gain/Range = 4 (Note 2) 0.490 (Note 3) (Note 3) 3 3 3300 4400 1100 275 69 0.515 1.05 1.95 5 5 0.540 5500 6 MIN TYP 128k 3.30 0.33 1 377 754 MAX UNIT lux V mA A kHz kHz kHz Counts Counts Counts Counts Counts Counts V V V mA mA
DESCRIPTION Maximum Detectable Light Intensity Power Supply Range Supply Current Supply Current Disabled Internal Oscillator Frequency Internal Oscillator Frequency I2C Clock Rate Dark ADC Code Full Scale ADC Code Light Count Output Light Count Output Light Count Output Light Count Output Voltage of REXT Pin SCL and SDA Threshold LO SCL and SDA Threshold HI SDA Current Sinking Capability INT Current Sinking Capability
2. Fluorescent light is substituted by a green LED during production. 3. The voltage threshold levels of the SDA and SCL pins are VDD dependent: VTL = 0.35*VDD. VTH = 0.65*VDD.
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ISL29012 Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 PIN NAME VDD GND REXT INT SCL SDA DESCRIPTION Positive supply; connect this pin to a regulated 2.5V to 3.3V supply. Ground pin. The thermal pad is connected to the GND pin. External resistor pin for ADC reference; connect this pin to ground through a (nominal) 100k resistor with 1% tolerance. Interrupt pin; LO for interrupt/alarming, open drain output. I2C serial clock I2C serial data The I2C bus lines can be pulled above VDD, 5.5V max.
Principles of Operation
Photodiodes
The ISL29012 contains two photodiode arrays which convert light into current. One diode (D1) is sensitive to both visible and infrared light, while the other one (D2) is only sensitive to infrared light; see Figure 21. Using the infrared portion of the light as a baseline, the visible light can be extracted. The ambient light output is the difference between D1 and D2. The resultant ALS spectral response vs wavelength is shown in Figure 7 in the "Typical Performance Curves" on page 11. After light is converted to current during the light data process, the current output is converted to digital by a single built-in integrating type signed 15-bit Analog-to-Digital Converter (ADC). An I2C command reads the visible light intensity in counts. The converter is a charge-balancing integrating type signed 15-bit ADC. The chosen method for conversion is best for converting small current signals in the presence of an AC periodic noise. A 100ms integration time, for instance, highly rejects 50Hz and 60Hz power line noise simultaneously. See "Integration Time or Conversion Time" on page 7 and "Noise Rejection" on page 8. The built-in ADC offers user flexibility in integration time or conversion time. There are two timing modes: Internal Timing Mode and External Timing Mode. In Internal Timing Mode, integration time is determined by an internal dual speed oscillator (fOSC), and the n-bit (n = 4, 8, 12,16) counter inside the ADC. In External Timing Mode, integration time is determined by the time between two consecutive I2C External Timing Mode commands. See "External Timing Mode" on page 7. A good balancing act of integration time and resolution depending on the application is required for optimal results. The ADC has four I2C programmable range selects to dynamically accommodate various lighting conditions. For very dim conditions, the ADC can be configured at its lowest range. For very bright conditions, the ADC can be configured at its highest range.
Interrupt Function
The active low interrupt pin is an open drain pull-down configuration. The interrupt pin serves as an alarm or monitoring function to determine whether the ambient light exceeds the upper threshold or goes below the lower threshold. The user can also configure the persistency of the interrupt pin. This helps to avoid false triggers, such as noise or sudden spikes in ambient light conditions. An unexpected camera flash, for example, can be ignored by setting the persistency to 8 integration cycles.
I2C Interface
There are eight (8) 8-bit registers available inside the ISL29012. The command and control registers define the operation of the device. The command and control registers do not change until the registers are overwritten. There are two 8-bit registers that set the high and low interrupt thresholds. There are four 8-bit data Read Only registers. Two bytes for the sensor reading and another two bytes for the timer counts. The data registers contain the ADC's latest digital output, and the number of clock cycles in the previous integration period. The ISL29012's I2C interface slave address is hardwired internally as 1000100. When 1000100x with x as R or W is sent after a START condition, this device compares the first 7 bits of this byte to its address and matches. Figure 1 shows a sample one-byte read. Figure 2 shows a sample one-byte write. Figure 3 shows a sync_I2C timing diagram sample for externally controlled integration time. The I2C bus master always drives the SCL (clock) line, while either the master or the slave can drive the SDA (data) line. Figure 2 shows a sample write. Every I2C transaction begins with the master asserting a start condition (SDA falling while SCL remains high). The following byte is driven by the master, and includes the slave address and read/write bit. The receiving device is responsible for pulling SDA low during the acknowledgement period. Every I2C transaction ends with the master asserting a stop condition (SDA rising while SCL remains high). For more information about the I2C standard, please consult the PhillipsTM I2C specification documents.
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ISL29012
I2C DATA
Start
DEVICE ADDRESS
W
A
REGISTER ADDRESS
A
STOP
START
DEVICE ADDRESS
A
DATA BYTE0
A
STOP
I2C SDA In
A6
A5
A4
A3
A2
A1
A0
W
A
R7
R6
R5
R4
R3
R2
R1
R0
A
A6
A5
A4
A3
A2
A1
A0
W
A
SDA DRIVEN BY ISL29003 ISL29012
NAK
I2C SDA Out
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A
D7
D6
D5
D4
D3
D2
D1
D0
A
I2C CLK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
FIGURE 1. I2C READ TIMING DIAGRAM SAMPLE
I2C DATA
Start
DEVICE ADDRESS
W
A
REGISTER ADDRESS
A
FUNCTIONS
A
STOP
I2C SDA In
A6 A5 A4 A3 A2 A1 A0
W
A
R7 R6 R5 R4 R3 R2 R1 R0
A
B7 B6 B5 B4 B3 B2 B1 B0
A
I2C SDA Out
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A
I2C CLK In
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
FIGURE 2. I2C WRITE TIMING DIAGRAM SAMPLE
I2 C D A T A
S t a rt
D E V IC E A D D R E S S
W
A
R E G IS T E R A D D R E S S
A S to p
I2 C S D A In
A6
A5
A4
A3
A2
A1
A0
W
A
R7
R6
R5
R4
R3
R2
R1
R0
A
I2 C S D A O u t
S D A D R IV EN B Y M A S T ER
A
S D A D R IV EN B Y M A S T ER
A
I2 C C L K In
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
FIGURE 3. I2C SYNC_I2C TIMING DIAGRAM SAMPLE
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ISL29012
Register Set
There are eight registers that are available in the ISL29012. Table 1 summarizes the available registers and their functions.
TABLE 1. REGISTER SET BIT ADDR 00h 01h 02h 03h 04h 05h 06h 07h REG NAME COMMAND CONTROL Interrupt Threshold_HI 7 ADCE 0 ITH_HI7 6 ADCPD 0 ITH_HI6 ITH_LO6 S6 S14 T6 T14 5 TIMM INT_FLAG ITH_HI5 ITH_LO5 S5 S13 T5 T13 4 0 0 ITH_HI4 ITH_LO4 S4 S12 T4 T12 3 ADCM1 GAIN1 ITH_HI3 ITH_LO3 S3 S11 T3 T11 2 ADCM0 GAIN0 ITH_HI2 ITH_LO2 S2 S10 T2 T10 1 RES1 IC1 ITH_HI1 ITH_LO1 S1 S9 T1 T9 0 RES0 IC0 ITH_HI0 ITH_LO0 S0 S8 T0 T8 DEFAULT 00h 00h FFh 00h 00h 00h 00h 00h
Interrupt ITH_LO7 Threshold_LO LSB SENSOR MSB SENSOR LSB TIMER MSB TIMER S7 S15 T7 T15
TABLE 2. WRITE ONLY REGISTERS REGISTER ADDRESS NAME b1xxx_xxxx sync_I2C FUNCTIONS/ DESCRIPTION Writing a logic 1 to this address bit ends the current ADC-integration and starts another. Used only with External Timing Mode. Writing a logic 1 to this address bit clears the interrupt. BIT 5 0 1
TABLE 5. TIMING MODE OPERATION Internal Timing Mode. Integration time is internally timed determined by fOSC, REXT, and number of clock cycles. External Timing Mode. Integration time is externally timed by the I2C host.
bx1xx_xxxx
clar_int
Command Register 00(hex)
The Read/Write command register has five functions: 1. Enable; Bit 7. This function either resets the ADC or enables the ADC in normal operation. A logic 0 disables ADC to reset-mode. A logic 1 enables ADC to normal operation.
TABLE 3. ENABLE BIT 7 0 1 OPERATION Disable ADC-core to reset-mode (default) Enable ADC-core to normal operation
4. Photodiode Select Mode; Bits 3 and 2. Setting Bit 3 and Bit 2 to 1 and 0 enables ADC to give light count DATA output.
TABLE 6. PHOTODIODE SELECT MODE; BITS 2 AND 3 BITS 3:2 0:0 0:1 1:0 1:1 Disable ADC Disable ADC Light count DATA output in signed (n-1) bit * No operation. MODE
* n = 4, 8, 12,16 depending on the number of clock cycles function. 5. Width; Bits 1 and 0. This function determines the number of clock cycles per conversion. Changing the number of clock cycles does more than just change the resolution of the device. It also changes the integration time, which is the period the device's analog-to-digital (A/D) converter samples the photodiode current signal for a lux measurement.
.
2. ADCPD; Bit 6. This function puts the device in a power-down mode. A logic 0 puts the device in normal operation. A logic 1 powers down the device.
TABLE 4. ADCPD BIT 6 0 1 OPERATION Normal operation (default) Power Down
TABLE 7. WIDTH BITS 1:0 0:0 0:1 1:0 1:1 NUMBER OF CLOCK CYCLES 216 = 65,536 212 = 4,096 28 = 256 24 = 16
3. Timing Mode; Bit 5. This function determines whether the integration time is done internally or externally. In Internal Timing Mode, integration time is determined by an internal dual speed oscillator (fOSC), and the n-bit (n = 4, 8, 12,16) counter inside the ADC. In External Timing Mode, integration time is determined by the time between three consecutive external-sync sync_I2C pulses commands. 5
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ISL29012
Control Register 01(hex)
The Read/Write control register has three functions: 1. Interrupt flag; Bit 5. This is the status bit of the interrupt. The bit is set to logic high when the interrupt thresholds have been triggered, and logic low when not yet triggered. Writing a logic low clears/resets the status bit.
TABLE 8. INTERRUPT FLAG BIT 5 0 1 OPERATION Interrupt is cleared or not triggered yet Interrupt is triggered
Sensor Data Register 04(hex) and 05(hex)
When the device is configured to output a signed 15-bit data, the most significant byte is accessed at 04(hex), and the least significant byte can be accessed at 05(hex). The sensor data register is refreshed after very integration cycle.
Timer Data Register 06(hex) and 07(hex)
Note that the timer counter value is only available when using the External Timing Mode. The 06(hex) and 07(hex) are the LSB and MSB respectively of a 16-bit timer counter value corresponding to the most recent sensor reading. Each clock cycle increments the counter. At the end of each integration period, the value of this counter is made available over the I2C. This value can be used to eliminate noise introduced by slight timing errors caused by imprecise external timing. Microcontrollers, for example, often cannot provide high-accuracy command-to-command timing, and the timer counter value can be used to eliminate the resulting noise.
TABLE 11. DATA REGISTERS ADDRESS (hex) 04 05 06 07 CONTENTS Least-significant byte of most recent sensor reading. Most-significant byte of most recent sensor reading. Least-significant byte of timer counter value corresponding to most recent sensor reading. Most-significant byte of timer counter value corresponding to most recent sensor reading.
2. Range/Gain; Bits 3 and 2. The Full Scale Range can be adjusted by an external resistor REXT and/or it can be adjusted via I2C using the Gain/Range function. Gain/Range has four possible values, Range(k) where k is 1 through 4. Table 9 lists the possible values of Range(k) and the resulting FSR for some typical value REXT resistors.
TABLE 9. RANGE/GAIN TYPICAL FSR LUX RANGES BITS 3:2 k RANGE(k) 0:0 0:1 1:0 1:1 1 2 3 4 2,000 8,000 32,000 128,000 FSR LUX RANGE@ REXT = 50k 2,000 8,000 32,000 128,000 FSR LUX FSR LUX RANGE@ RANGE@ REXT = 100k REXT = 500k 1,000 4,000 16,000 64,000 200 800 3200 12,800
Interrupt persist; Bits 1 and 0. The interrupt pin and the interrupt flag is triggered/set when the data sensor reading is out of the interrupt threshold window after m consecutive number of integration cycles. The interrupt persist bits determine m.
TABLE 10. INTERRUPT PERSIST BITS 1:0 0:0 0:1 1:0 1:1 NUMBER OF INTEGRATION CYCLES 1 4 8 16
Calculating Lux
The ISL29012's output codes, DATA, are directly proportional to lux.
E = x DATA (EQ. 1)
The proportionality constant is determined by the Full Scale Range (FSR), and the n-bit ADC which is user defined in the command register. The proportionality constant can also be viewed as the resolution; The smallest lux measurement the device can measure is .
FSR = -----------n 2 (EQ. 2)
Interrupt Threshold HI Register 02(hex)
This register sets the HI threshold for the interrupt pin and the interrupt flag. By default the Interrupt threshold HI is FF(hex). The 8-bit data written to the register represents the upper MSB of a 16-bit value. The LSB is always 00(hex).
Full Scale Range (FSR), is determined by the software programmable Range/Gain, Range(k), in the command register and an external scaling resistor REXT which is referenced to 100k.
100k FSR = Range ( k ) x ----------------R EXT (EQ. 3)
Interrupt Threshold LO Register 03(hex)
This register sets the LO threshold for the interrupt pin and the interrupt flag. By default, the Interrupt threshold LO is 00(hex). The 8-bit data written to the register represents the upper MSB of a 16-bit value. The LSB is always 00(hex).
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ISL29012
The transfer function effectively for each timing mode becomes:
INTERNAL TIMING MODE 100k Range ( k ) x ----------------R EXT E = ---------------------------------------------------- x DATA n 2 EXTERNAL TIMING MODE 100k Range ( k ) x ----------------R EXT E = ---------------------------------------------------- x DATA COUNTER (EQ. 5) (EQ. 4) n 15 11 7 3 TABLE 12. RESOLUTION AND INTEGRATION TIME SELECTION RANGE1 fOSC = 327kHz tINT (ms) 200 12.8 0.8 0.05 RESOLUTION LUX/COUNT 0.06 1.0 15.6 250 RANGE4 fOSC = 655kHz tINT (ms) 100 6.4 0.4 0.025 RESOLUTION (LUX/COUNT) 2 62.5 1,000 16,000
n = 3, 7, 11, or 15. This is the number of clock cycles programmed in the command register. Range(k) is the user defined range in the Gain/Range bit in the command register. REXT is an external scaling resistor hardwired to the REXT pin. DATA is the output sensor reading in number of counts available at the data register. 2n represents the maximum number of counts possible in Internal Timing Mode. For the External Timing Mode the maximum number of counts is stored in the data register named COUNTER. COUNTER is the number increments accrued for between integration time for External Timing Mode.
REXT = 100k
External Scaling Resistor REXT and fOSC The ISL29012 uses an external resistor REXT to fix its internal oscillator frequency, fOSC. Consequently, REXT determines the fOSC, integration time and the FSR of the device. fOSC, a dual speed mode oscillator, is inversely proportional to REXT. For user simplicity, the proportionality constant is referenced to fixed constants 100k and 655kHz in Equations 6 and 7:
1 100k f OSC 1 = -- x ----------------- x 684 kHz 2 R EXT 100k f OSC 2 = ----------------- x 684 kHz R EXT (EQ. 6)
(EQ. 7)
Gain/Range, Range(k)
The Gain/Range can be programmed in the control register to give Range(k) determining the FSR. Note that Range(k) is not the FSR (see Equation 3). Range(k) provides four constants depending on programmed k that will be scaled by REXT (see Table 9). Unlike REXT, Range(k) dynamically adjusts the FSR. This function is especially useful when light conditions are varying drastically while maintaining excellent resolution.
fOSC1 is oscillator frequency when Range1 or Range2 are set. This is nominally 342kHz when REXT is 100k. fOSC2 is the oscillator frequency when Range3 or Range4 are set. This is nominally 684kHz when REXT is 100k. When the Range/Gain bits are set to Range1 or Range2, fOSC runs at half speed compared to when Range/Gain bits are set to Range3 and Range4 by using Equation 8:
1 f OSC 1 = -- ( f OSC 2 ) 2 (EQ. 8)
Number of Clock Cycles, n-bit ADC
The number of clock cycles determines "n" in the n-bit ADC; 2n clock cycles is a n-bit ADC. n is programmable in the command register in the width function. Depending on the application, a good balance of speed, and resolution has to be considered when deciding for n. For fast and quick measurement, choose the smallest n = 3. For maximum resolution without regard of time, choose n = 15. Table 12 compares the trade-off between integration time and resolution. See Equations 10 and 11 for the relation between integration time and n. See Equation 3 for the relation of n and resolution.
The automatic fOSC adjustment feature allows significant improvement of signal-to-noise ratio when detecting very low lux signals.
Integration Time or Conversion Time
Integration time is the period during which the device's analog-to-digital ADC converter samples the photodiode current signal for a lux measurement. Integration time, in other words, is the time to complete the conversion of analog photodiode current into a digital signal--number of counts. Integration time affects the measurement resolution. For better resolution, use a longer integration time. For short and fast conversions, use a shorter integration time. The ISL29012 offers user flexibility in the integration time to balance resolution, speed and noise rejection. Integration time can be set internally or externally and can be programmed in the command register 00(hex) Bit 5.
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ISL29012
Integration time in Internal Timing Mode
This timing mode is programmed in the command register 00(hex) Bit 5. Most applications will be using this timing mode. When using the Internal Timing Mode, fOSC and n-bits resolution determine the integration time. tINT is a function of the number of clock cycles and fOSC as shown in Equation 9:
t INT = 2
m
count DATA, and starts over again to commence conversion of diode array 1. The integration time, tINT, is the sum of two identical time intervals between the three sync pulses. tINT is determined by Equation 12:
k OSC t INT = -------------f OSC (EQ. 12)
1 x ---------f osc
for Internal Timing Mode only
(EQ. 9)
m = 4, 8, 12, and16. n is the number of bits of resolution. 2m therefore is the number of clock cycles. n can be programmed at the command register 00(hex) Bits 1 and 0. Since fOSC is dual speed depending on the Gain/Range bit, tINT is dual time. The integration time as a function of REXT is shown in Equation 10:
t INT 1 = 2
m
where KOSC is the number of internal clock cycles obtained from Timer data register and fOSC is the internal I2C operating frequency The internal oscillator, fOSC, operates identically in both the internal and external timing modes, with the same dependence on REXT. However, in External Timing Mode, the number of clock cycles per integration is no longer fixed at 2n. The number of clock cycles varies with the chosen integration time, and is limited to 216 = 65,536. In order to avoid erroneous lux readings, the integration time must be short enough not to allow an overflow in the counter register.
65,535 t INT < ----------------f OSC (EQ. 13)
R EXT x --------------------------------------------342kHz x 100k
(EQ. 10)
tINT1 is the integration time when the device is configured for Internal Timing Mode and Gain/Range is set to Range1 or Range2.
t INT 2 = 2
m
R EXT x --------------------------------------------684kHz x 100k
(EQ. 11)
fOSC = 342kHz*100k/REXT. When Range/Gain is set to Range1 or Range2. fosc = 684kHz*100k/REXT. When Range/Gain is set to Range3 or Range4.
tINT2 is the integration time when the device is configured for Internal Timing Mode and Gain/Range is set to Range3 or Range4.
TABLE 13. INTEGRATION TIMES FOR TYPICAL REXT VALUES RANGE1 RANGE2 n = 15-BIT 100 200 400 1000 n = 11-BIT 6.4 13 26 64 RANGE3 RANGE4 n = 11-BIT 3.2 6.5 13 32 n=3 0.013 0.025 0.050 0.125
Noise Rejection
In general, integrating type ADC's have excellent noise-rejection characteristics for periodic noise sources whose frequency is an integer multiple of the integration time. For instance, a 60Hz AC unwanted signal's sum from 0ms to k*16.66ms (k = 1,2...ki) is zero. Similarly, setting the device's integration time to be an integer multiple of the periodic noise signal, greatly improves the light sensor output signal in the presence of noise.
REXT (k) 50 100** 200 500
Ambient Light Sensing Operation
The operation of ambient light sensing (ALS) within the ISL29012 utilizes two diodes; D1 and D2. The D1 diode is sensitive to both visible and IR light spectrum. The D2 diode is sensitive to IR spectrum. D1 and D2 spectrum response is shown in Figure 21. The diodes are measured sequentially and their outputs are converted with an ADC. The output of the ALS is the difference between these two measurements.
*Integration time in milliseconds **Recommended REXT resistor value
Integration time in External Timing Mode
This timing mode is programmed in the command register 00(hex) Bit 5. External Timing Mode is recommended when integration time can be synchronized to an external signal such as a PWM to eliminate noise. To read the light count DATA output, the device needs three sync_I2C commands to complete one measurement. The 1st sync_I2C command starts the conversion of the diode array 1. The 2nd sync_I2C completes the conversion of diode array 1 and starts the conversion of diode array 2. The 3rd sync_I2C pules ends the conversion of diode array 2, outputs the light
Maximum Ambient Intensity Condition
In typical applications, the ISL29012 is installed behind a dark cover window. In this low-light condition, both D1 and D2 operate linearly and the ALS output is linear as well (Figures 19 and 20). In brighter environments and with transparent glass, however, D1 and D2 can be subject to saturation. As the ambient light grows bright enough to subject one or both diodes to saturation, the ALS count (output) decreases and eventually reaches zero in deep
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8
ISL29012
saturation (Figure 18). When using the ISL29012 in high lux applications, one can reduce the REXT value and select Range4, the lowest gain to avoid saturation. For example, REXT = 25k is recommended with ambient light near 100,000 lux. If you are operating the ISL29012 at a lower range/higher gain and detect a zero output, the firmware should change the range and recheck the ALS count. One of two situations will be identified. If the output is non-zero, the ISL29012 is saturated. If the output remains zero, the ISL29012 is in a totally dark environment.
.
WINDOW LENS
t
DTOTAL D1
ISL29012
ALS Range For Various Light Sources
Figure 9 shows spectrum response of various light sources. Fluorescent has little IR content while sunlight, halogen and incandescent light have large IR content. Since both the internal photo diodes D1 and D2 are sensitive to IR spectrum, they saturate at a higher level for the fluorescent light source in comparison to the other 3 light sources. This effect is shown in Figure 22.
E= DATA 215 x 2000
DLENS
= VIEWING ANGLE
FIGURE 4. FLAT WINDOW LENS TABLE 14. RECOMMENDED DIMENSIONS FOR A FLAT WINDOW DESIGN DTOTAL 1.5 2.0 2.5 3.0 3.5 t=1 d1 DLENS dTOTAL D1 0.50 1.00 1.50 2.00 2.50 DLENS @ 35 VIEWING ANGLE 2.25 3.00 3.75 4.30 5.00 DLENS @ 45 VIEWING ANGLE 3.75 4.75 5.75 6.75 7.75
Unstable Ambient Light Condition
The ISL29012 sequentially measures the difference in the output of two diodes. That's suitable since most changes in ambient light are gradual and any difference between the ambient light conditions for D1 and D2 are negligible. However, it is possible to cause an abrupt change in brightness with a fast-moving hand over the sensor or passing a tree shadow in a fast moving car. To handle these anomalies, we suggest comparing several sequential readings and discarding any data with sudden changes.
Flat Window Lens Design
A window lens will surely limit the viewing angle of the ISL29012. The window lens should be placed directly on top of the device. The thickness of the lens should be kept at minimum to minimize loss of power due to reflection and also to minimize loss of loss due to absorption of energy in the plastic material. A thickness of t = 1mm is recommended for a window lens design. The bigger the diameter of the window lens the wider the viewing angle is of the ISL29012. Table 14 shows the recommended dimensions of the optical window to ensure both 35 and 45 viewing angle. These dimensions are based on a window lens thickness of 1.0mm and a refractive index of 1.59.
Thickness of lens Distance between ISL29012 and inner edge of lens Diameter of lens Distance constraint between the ISL29012 and lens outer edge
* All dimensions are in mm.
Window with Light Guide Design
If a smaller window is desired while maintaining a wide effective viewing angle of the ISL29012, a cylindrical piece of transparent plastic is needed to trap the light and then focus and guide the light on to the device. Hence, the name light guide or also known as light pipe. The pipe should be placed directly on top of the device with a distance of d1 = 0.5mm to achieve peak performance. The light pipe should have a minimum of 1.5mm in diameter to ensure that whole area of the sensor will be exposed. See Figure 5.
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FN6476.1 December 10, 2008
ISL29012
DLENS
D2 > 1.5mm LIGHT PIPE
t D2 DLENS
L
ISL29012
FIGURE 5. WINDOW WITH LIGHT GUIDE/PIPE
Suggested PCB Footprint
It is important that the users check the "Surface Mount Assembly Guidelines for Optical Dual FlatPack No Lead (ODFN) Package" before starting ODFN product board mounting. http://www.intersil.com/data/tb/TB477.pdf
Typical Circuit
A typical application for the ISL29012 is shown in Figure 6. The ISL29012's I2C address is internally hardwired as 1000100. The device can be tied onto a system's I2C bus together with other I2C compliant devices.
Soldering Considerations
Convection heating is recommended for reflow soldering; direct-infrared heating is not recommended. The plastic ODFN package does not require a custom reflow soldering profile, and is qualified to +260C. A standard reflow soldering profile with a +260C maximum is recommended.
Layout Considerations
The ISL29012 is relatively insensitive to layout. Like other I2C devices, it is intended to provide excellent performance even in significantly noisy environments. There are only a few considerations that will ensure best performance. Route the supply and I2C traces as far as possible from all sources of noise. Use one 0.01F power-supply decoupling capacitor, placed close to the device.
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FN6476.1 December 10, 2008
ISL29012
2.5V TO 5.5V R1 10k R2 10k R3 RES1 I2C MASTER MICROCONTROLLER SDA SCL INT
2.5V TO 3.3V
I2C SLAVE_0 1 2 C1 0.01F 3 REXT 100k VDD GND REXT SDA SCL INT 6 5 4
I2C SLAVE_1 SDA SCL
I2C SLAVE_n SDA SCL
ISL29012
FIGURE 6. ISL29012 TYPICAL CIRCUIT
Typical Performance Curves (REXT = 100k)
1.2 HUMAN EYE RESPONSE NORMALIZED RESPONSE 1.0 20 0.8 0.6 0.4 0.2 0.0 -0.2 ISL29012 RESPONSE 60 70 80 90 300 400 600 800 WAVELENGTH (nm) 1.0k 1.1k 0.2 0.4 0.6 0.8 RELATIVE SENSITIVITY LUMINOSITY 30 ANGLE 40 50 RADIATION PATTERN 10 0 10 20 30 40 50 60 70 80 90 1.0
FIGURE 7. SPECTRAL RESPONSE
FIGURE 8. RADIATION PATTERN
1.2 NORMALIZED LIGHT INTENSITY 1.0 SUN 0.8 HALOGEN 0.6 0.4 0.2 0 300 INCANDESCENT FLUORESCENT SUPPLY CURRENT (A)
320 TA = +27C 306 5000 lux 292
278 200 lux 264
400
500
600
700
800
900
1000
1100
250 2.0
2.3
2.6
2.9
3.2
3.5
3.8
WAVELENGTH (nm)
SUPPLY VOLTAGE (V)
FIGURE 9. SPECTRUM OF LIGHT SOURCES FOR MEASUREMENT
FIGURE 10. SUPPLY CURRENT vs SUPPLY VOLTAGE
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FN6476.1 December 10, 2008
ISL29012 Typical Performance Curves (REXT = 100k)
10 TA = +27C 0 lux OUTPUT CODE RATIO (% FROM 3V) 8
(Continued)
1.015 TA = +27C 1.010 5000 lux 1.005
OUTPUT CODE (COUNTS)
6
4 RANGE 2 2
1.000 200 lux
0.995
0 2.0
2.3
2.6
2.9
3.2
3.5
3.8
0.990 2.0
2.3
2.6
2.9
3.2
3.5
3.8
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 11. OUTPUT CODE FOR 0 LUX vs SUPPLY VOLTAGE
FIGURE 12. OUTPUT CODE vs SUPPLY VOLTAGE
320.0 OSCILLATOR FREQUENCY (kHz) TA = +27C 319.5 SUPPLY CURRENT (mA)
315 VDD = 3V 305 5000 lux RANGE 3 295
319.0
285 200 lux RANGE 1 275
318.5
318.0 2.0
2.3
2.6
2.9
3.2
3.5
3.8
265 -60
-20
20 TEMPERATURE (C)
60
100
SUPPLY VOLTAGE (V)
FIGURE 13. OSCILLATOR FREQUENCY vs SUPPLY VOLTAGE
FIGURE 14. SUPPLY CURRENT vs TEMPERATURE
10 VDD = 3V OUTPUT CODE (COUNTS) OUTPUT CODE RATIO (% FROM +25C) 8 0 lux
1.080 VDD = 3V 1.048 5000 lux RANGE3 1.016 200 lux RANGE1
6
4 RANGE 2
0.984
2
0.952
0 -60
-20
20 TEMPERATURE (C)
60
0.920 -60
-20
20 TEMPERATURE (C)
60
100
FIGURE 15. OUTPUT CODE FOR 0 LUX vs TEMPERATURE
FIGURE 16. OUTPUT CODE vs TEMPERATURE
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FN6476.1 December 10, 2008
ISL29012 Typical Performance Curves (REXT = 100k)
330 OSCILLATOR FREQUENCY (kHz) VDD = 3V 329 ADC READING (COUNTS) 10k ALS RANGE 4 8k 6k 4k 2k 0 100 0 20k 40k 60k 80k 100k 120k LUX METER READING (LUX), SUN LIGHT
(Continued)
12k ALS RANGE 3
328
327
326
325 -60
-20
20 TEMPERATURE (C)
60
FIGURE 17. OSCILLATOR FREQUENCY vs TEMPERATURE
FIGURE 18. SATURATION CHARACTERISTICS
1000 CALCULATED ALS READING (LUX) 900 800 700 600 500 400 300 200 100 0 0
CALCULATED ALS READING (LUX)
VDD = 3V HALOGEN
100 90 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 LUX METER READING (LUX) INCANDESCENT FLUORESCENT VDD = 3V HALOGEN
INCANDESCENT FLUORESCENT
100
200
300
400
500
600
700
800
900
1k
LUX METER READING (LUX)
FIGURE 19. LIGHT SENSITIVITY vs LUX LEVEL
FIGURE 20. LIGHT SENSITIVITY vs LUX LEVEL
1.2 HUMAN EYE RESPONSE NORMALIZED RESPONSE 1.0 0.8 0.6 0.4 0.2 0 -0.2 300 400 500 600 700 800 900 1000 1100 WAVELENGTH (nm) INTERNAL D1 INTERNAL D2 ALS OUTPUT (D1 - D2)
18000 16000 14000 12000 10000 8000 6000 HALOGEN 4000 2000 0
00 30 00 28 00 26 00 24 00 22 00 20 00 18 00 16 00 14 00 12 00 10 0 80 0 60 0 40 0 20 0
FLUORESCENT
SUNLIGHT
INCANDESCENT
LUX METER READING (LUX)
FIGURE 21. SPECTRAL RESPONSE INTERNAL DIODES
FIGURE 22. ALS OUTPUT vs LUX LEVEL @ RANGE = 1, REXT = 50k
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FN6476.1 December 10, 2008
ISL29012
2.10mm
VDD
1
6
SDA
2.00mm 0.29mm
GND
2
5
SCK
0.56mm
REXT
3
4
INT
0.43mm
FIGURE 23. 6 LD ODFN SENSOR LOCATION OUTLINE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
FN6476.1 December 10, 2008
ISL29012
Package Outline Drawing
L6.2x2.1
6 LEAD OPTICAL DUAL FLAT NO-LEAD PLASTIC PACKAGE (ODFN) Rev 0, 9/06
2.10 A
6 PIN 1 INDEX AREA
B
1
6 PIN 1 INDEX AREA 0.65 2.00
1 . 35
1 . 30 REF
(4X)
0.10
6X 0 . 30 0 . 05
0 . 65
TOP VIEW
0.10 M C A B 6X 0 . 35 0 . 05
BOTTOM VIEW
(0 . 65) MAX 0.75 SEE DETAIL "X" 0.10 C (0 . 65) (1 . 35) BASE PLANE ( 6X 0 . 30 ) SIDE VIEW SEATING PLANE 0.08 C C
( 6X 0 . 55 ) C (1 . 95) 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" 0 . 2 REF 5
TYPICAL RECOMMENDED LAND PATTERN
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
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FN6476.1 December 10, 2008

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